A novel capacitive-coupled floating gate antenna protection design and its application to prevent in-process charging effects for 3D NAND flash memory

In-process charging effect is found to deteriorate the initial Vt distribution of 3D NAND Flash. In this work, we propose a novel antenna protection circuit using a capacitive coupled floating gate (CCFG) CMOS circuit that can be applied to the word line (WL), string select (SSL) and ground select transistor (GSL) decoders. Experimental results show a very low turn-on voltage (<; +/-2V) for discharging, providing ideal protection for the memory devices. With this novel technique, our fully-integrated 3D NAND Flash device shows excellent initial Vt distribution free from the charging effect. Furthermore, the impact of SSL Vt distribution on the minimal Vdd bias is studied. With optimal SSL Vt distribution, it is demonstrated that 3D VG NAND Flash can support Vdd as low as 1.6V with successful programming window.