Title :
What can we do about barrier layer scaling to 5 nm node technology ?
Author_Institution :
Dept. of Mater. Sci., Tohoku Univ., Sendai, Japan
Abstract :
Interconnect-related problems in the advanced technology node are identified and possible solutions are proposed. A PVD process of a double-layer Ta/TaN barrier is to be replaced with a CVD process of a single-layer barrier. Cu filling process can be changed from PVD seed deposition and electroplating to dynamic PVD reflow of Cu. Manganese and its oxide are shown as a possible choice of new barrier materials.
Keywords :
copper; electroplating; semiconductor device metallisation; semiconductor device reliability; tantalum compounds; CVD process; Cu; PVD process; PVD reflow; PVD seed deposition; Ta-TaN; barrier layer scaling; double layer barrier; electroplating; single layer barrier; size 5 nm; Filling; Manganese; Materials; Reliability; Sputtering; Surface treatment;
Conference_Titel :
VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3331-0
DOI :
10.1109/VLSIT.2014.6894408
