Title :
10 bit, 25 MBz, 15 mW CMOS pipelined subranging ADC
Author :
Dong, Shang-Ching ; Carlson, Bradley S.
Author_Institution :
Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
Abstract :
A new scheme to implement the pipelined subranging ADC is presented in this paper. Source follower structured subtractors and latch structured comparators enable the ADC to operate at 25 MHz sampling rate with very low power dissipation. Higher sampling rate is achievable with the trade-off of power consumption. The maximum resolution is 10 bits. The circuits can also be used in 3-V powered systems. The die area is less than 0.36 mm2 in 0.8 μm process
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); integrated circuit design; pipeline processing; 10 bit; 15 mW; 25 MHz; CMOS; die area; latch structured comparators; pipelined subranging ADC; power dissipation; resolution; sampling rate; source follower structured subtractors; Circuits; Dynamic range; Energy consumption; Latches; Operational amplifiers; Power dissipation; Sampling methods; Signal processing; Switches; Voltage;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.621552
