A build-up substrate utilizing a new via fill technology by electroplating

A build-up substrate consisting of PPE resin (poly-phenylene ether) was developed to mount high pin count flip chips. It is essential to achieve high density patterns with controlled characteristic impedance for MPU packages and telecommunication devices. Via fill technology by electroplating incorporated with new via designs is effective for this application. Stacked via design and the technology to fill the via are an essential part of the technology for future packages. It is effective to stabilize the power supply to the chip since it shortens the continuum of the chip to substrate. To realize the micro via filling, a new copper electrolytic plating solution and plating method were investigated. The copper solution used for via fill contains chloride ions, polyester type polymers, sulfur-containing brighteners and dyes as additives. It was confirmed that the adsorption behavior of the additives, agitation strength and current waveform for the plating influenced strongly the via filling phenomena. The optimum plating conditions for the large boards were determined and the micro vias on the large boards were confirmed well filled with copper electroplating. The mechanism of the via filling was explained based on the data of the electrochemical measurements, SEM observation and relevant information available in the literature