DocumentCode
230494
Title
Monolithic three-dimensional integration of carbon nanotube FETs with silicon CMOS
Author
Shulaker, Max M. ; Saraswat, Krishna ; Wong, H.-S Philip ; Mitra, Subhasish
Author_Institution
Stanford Univ., Stanford, CA, USA
fYear
2014
fDate
9-12 June 2014
Firstpage
1
Lastpage
2
Abstract
We demonstrate the first VLSI-compatible approach for monolithic three-dimensional (3D) integration of carbon nanotube field effect transistors (CNFETs) with silicon CMOS for high-performance digital logic applications. Fine-grained monolithic 3D integration is demonstrated at the logic gate level, whereby individual logic gates are composed of both CNFETs and silicon FETs. Monolithic 3D integration is additionally achieved at the circuit-level, with CNFET logic gates cascaded with silicon CMOS logic gates, creating hybrid CNFET-silicon CMOS logic circuits. All the CNFET fabrication steps are VLSI-scalable and silicon CMOS compatible. CNFET fabrication is performed after the silicon CMOS processing is completed and the CNFETs directly overlap on top of the silicon FETs. This work demonstrates both the compatibility of CNFETs with silicon CMOS and the ability to achieve monolithic 3D ICs simultaneously using silicon CMOS and CNFETs.
Keywords
CMOS logic circuits; VLSI; carbon nanotube field effect transistors; integrated circuit interconnections; three-dimensional integrated circuits; CNFET logic gates; VLSI; carbon nanotube FET; digital logic applications; hybrid CNFET-silicon CMOS logic circuits; monolithic 3D IC; monolithic 3D integration; silicon CMOS logic gates; silicon FET; CMOS integrated circuits; CNTFETs; Inverters; Logic gates; Silicon; Three-dimensional displays;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on
Conference_Location
Honolulu, HI
ISSN
0743-1562
Print_ISBN
978-1-4799-3331-0
Type
conf
DOI
10.1109/VLSIT.2014.6894422
Filename
6894422
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