Title :
Design methodology of tri-gate poly-Si MOSFETs with 10nm nanowire channel to enhance short-channel performance and reduce Vth & Id variability
Author :
Saitoh, Masatoshi ; Ota, Kaoru ; Tanaka, C. ; Numata, T.
Author_Institution :
Adv. LSI Technol. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
We present the optimum design of tri-gate poly-Si nanowire transistors (NW Tr.) based on the systematic performance and variability analysis for various NW width (WNW) and thickness (TSi) down to 10nm. Ion difference between poly-Si and crystalline-Si Tr. at short L (down to 25nm) is much smaller than long L due to poly-Si defect-barrier lowering by high lateral field. Ion of poly-Si pFETs is close to nFETs due to smaller interface defects. Both WNW and TSi scaling reduces S factor, SCE and Avt (Vth & Id variations) caused by random grain placement. Avt of thin poly-Si Tr. falls even below doped bulk Tr. Since short-NW Tr. suffers from high RSD and low μ, narrow and tall poly-Si NW Tr. is the best for 3D CMOS.
Keywords :
MOSFET; crystal defects; nanowires; silicon; 3D CMOS; NW Tr design methodology; NW scaling; NW width; Si; crystalline-Si Tr; doped bulk Tr; high lateral field; interface defect; nFET; nanowire channel; polySi defect-barrier; polySi pFET; random grain placement; short-channel performance; size 10 nm; trigate polySi MOSFET; variability analysis; CMOS integrated circuits; Grain boundaries; Grain size; Impurities; Logic gates; Silicon; Three-dimensional displays;
Conference_Titel :
VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3331-0
DOI :
10.1109/VLSIT.2014.6894425
