A micropower current-mode pattern-matching classifier circuit using FG-MOS transistors

In this paper an analog template-based pattern classifier circuit based on a new synthesis of Euclidean distance calculation is presented. It is composed of simple two-quadrant squarer/divider blocks. The circuit that employs floating gate MOS (FG-MOS) transistors operating in weak inversion region, features low circuit complexity, low power (20 uW), low supply voltage (0.5 V), two quadrant input current, wide dynamic range and immunity from body effect. In addition, this classifier circuit is designed in modular methodology, leading to a very regular structure. The circuit was successfully applied to the recognition of some simple patterns. Simulation results by HSPICE show high performance in the separation and classification of circuit.