Feasibility study on through-wafer interconnecting method for hybrid wafer-scale-integration

Author

Fujita, Yoshikazu ; Kawamura, Yuriko ; Mizuishi, K.

Author_Institution

Hitachi Ltd., Tokyo

fYear

1993

fDate

1-4 Jun 1993

Firstpage

1081

Lastpage

1084

Abstract

A novel soldering technique for connecting input/output (I/O) pins on the back side of the wafer is described. After the preforms between the through-holes etched into the silicon wafer and the I/O pins are melted in vacuum (about 1 torr), the vacuum is released to make the solder flow into the through-hole area, soldering the I/O pins to the metallization layer on the active devices. This process provides reliable and highly conductive metal interconnection through the wafer because a virtually voidless solder layer is formed without the use of flux. The percentage of void-free through-holes is 95%, and the resistance of each through-hole is 10-15 mΩ. It is demonstrated that this method provides ideal interconnections for hybrid wafer-scale integration

Keywords

hybrid integrated circuits; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; reflow soldering; wafer-scale integration; I/O pins; hybrid wafer-scale-integration; metal interconnection; soldering technique; through-hole area; through-wafer interconnecting method; void-free through-holes; voidless solder layer; Etching; Integrated circuit interconnections; Joining processes; Metallization; Pins; Preforms; Propagation delay; Silicon; Soldering; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 1993. Proceedings., 43rd

Conference_Location

Orlando, FL

Print_ISBN

0-7803-0794-1

Type

conf

DOI

10.1109/ECTC.1993.346701

Filename

346701