Lead-on-chip technology for high performance packaging

The modeling and simulation efforts for the development of a lead-over-chip (LOC) style package for 16 Mb dynamic random access memories is described. Electrical models and simulation address the effects of power bus noise and the interaction of chip conductors with the LOC lead frame. The thermomechanical stress issues in the LOC package are modeled using finite element techniques to optimize the design and material properties to avoid damage to the chip or package during fabrication and testing. For surface mount components, stress from the reflow process resulting from vapor pressure concentrated at points of delamination must also be comprehended and minimized. Thermal analysis of the LOC package was performed using finite element analysis and measurements, and the data were compared to those of standard packaging designs