Title :
Phase locked loop using delay compensation techniques
Author_Institution :
Storage Product Group, Texas Instrum., San Jose, CA, USA
Abstract :
This paper illustrates a modification to a basic phase locked loop (PLL) topology aimed at compensating the effects of loop latency. The technique, developed to address the performance degradation observed in high latency PLL topologies as is the case of Viterbi based decision directed read channel timing recovery, is readily applicable to digital baseband communication receivers
Keywords :
delays; digital communication; disc drives; hard discs; network topology; phase locked loops; synchronisation; Hard Disk Drive; ISI; PLL topology; Viterbi based timing recovery; delay compensation techniques; digital baseband communication receivers; directed read channel timing recovery; intersymbol interference; loop latency; partial response maximum-likelihood; performance degradation; phase locked loop; Circuit topology; Clocks; Delay; Detectors; Filters; Intersymbol interference; Maximum likelihood detection; Maximum likelihood estimation; Phase locked loops; Timing;
Conference_Titel :
Computers and Communications, 2000. Proceedings. ISCC 2000. Fifth IEEE Symposium on
Conference_Location :
Antibes-Juan les Pins
Print_ISBN :
0-7695-0722-0
DOI :
10.1109/ISCC.2000.860673
