A threshold voltage model for DMG-MOS transistors taking into account the varying depth of channel depletion layers around the source and drain

In this paper, an analytical model for threshold voltage of dual material gate (DMG) MOS transistors is presented. For such devices, the depletion regions due to source/drain junctions occupy a large portion of the channel, and hence are very important for accurate modeling. The proposed threshold voltage model is based on a realistic physically-based model for the depletion layer depth along the channel that takes into account its variation due to the source and drain junctions as well as the work function difference of the metal gate materials. The proposed model can predict the drain induced barrier lowering (DIBL) effect and hence, the threshold voltage roll-off characteristics quite accurately. The model predictions are verified against the 2-D numerical device simulator, DESSIS of ISE TCAD.