Title :
Noise in deep submicron digital design
Author :
Shepard, K.L. ; Narayanan, V.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of VLSI systems. This paper defines noise as it pertains to digital systems and addresses the technology trends which are bringing noise issues to the forefront. The noise sources which are plaguing digital systems are explained. A metric referred to as noise stability is defined, and a static noise analysis methodology based on this metric is introduced to demonstrate how noise can be analyzed systematically. Analysis issues associated with on-chip interconnect are also considered. This paper concludes with a discussion of the device, circuit, layout, and logic design issues associated with noise.
Keywords :
VLSI; circuit layout CAD; integrated circuit interconnections; logic CAD; noise; timing; VLSI systems; area; deep submicron digital design; logic design; noise immunity; noise stability; on-chip interconnect; power; technology trends; timing; 1f noise; CMOS logic circuits; Circuit noise; Digital circuits; Digital systems; Impedance; Logic circuits; Noise reduction; Threshold voltage; Timing;
Conference_Titel :
Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-7597-7
DOI :
10.1109/ICCAD.1996.569906
