Analysis of the stresses in the chip´s coating

Microelectronic packages have been widely used in the last decade, and their capabilities and performance have improved significantly; however, there is still a great deal of concern with the reliability of the packages. To protect the silicon chip from the moisture and ensure electrical performance of the packages, coating materials have been applied. During the coating procedure, the silicon chip and coating material are usually heated to a high temperature. After the coating is applied, the device is then cooled. The mechanical stresses are created in both the chip and the coating because of mismatch in the coefficients of thermal expansion. The coating may fail because mechanical stresses exceed the critical value, therefore, proper evaluation of the stress state becomes very important. Thus, the objective of this work was to utilize an experimental method of Digital Image Analysis Enhanced Moire Interferometry (DIAEMI) to investigate these stresses. This technique monitors the actual out-of-plane displacements of the chip due to the application of the coating and it can operate on small samples. The specimens were prepared from the 0.5 mm thick silicon wafer. The moire patterns of the specimens were recorded both before and after the application of the coating. The results from the obtained moire patterns show that the significant mechanical stresses were developed in the coating and that in the thicker coating, higher stresses are induced