DocumentCode
2307088
Title
Rapid yield estimation as a computer aid for analog cell design
Author
Mukherjee, Tamal ; Carley, L.
Author_Institution
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear
1990
fDate
13-16 May 1990
Abstract
A rapid yield estimation methodology that aids the analog circuit designer in making design tradeoffs that improve yield is presented. ARYE (analog rapid yield estimator), a CAD tool that implements this methodology for op-amps, has been incorporated into ACACIA, the CMU analog design system, in order to allow analog designers to quickly explore the impact of design changes on yield. A design example using ARYE and ACACIA to enhance the yield of a two-stage op-amp design is presented
Keywords
analogue circuits; circuit CAD; linear integrated circuits; operational amplifiers; ACACIA; ARYE; CAD tool; CMU analog design system; analog cell design; analog rapid yield estimator; design tradeoffs; op-amps; two-stage op-amp design; yield estimation methodology; Analog circuits; Analog computers; Application specific integrated circuits; Digital circuits; Fabrication; Integrated circuit yield; Manufacturing; Operational amplifiers; Performance loss; Yield estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location
Boston, MA
Type
conf
DOI
10.1109/CICC.1990.124690
Filename
124690
Link To Document