An approach towards improved cyber security by hardware acceleration of OpenSSL cryptographic functions

Providing improved Information Security to the rapidly developing Cybernet System has become a vital factor in the present technically networked world. The information security concept becomes a more complicated subject when the more sophisticated system requirements and real time computation speed are considered. In order to solve these issues, lots of research and development activities are carried out and cryptography has been a very important part of any communication system in the recent years. Cryptographic algorithms fulfil specific information security requirements such as data integrity, confidentiality and authenticity. This work proposes an FPGA-based VLSI Crypto-System, integrating hardware that accelerates the cryptographic algorithms used in the SSL/TLS protocol. SSL v3 and TLS v1 protocol is deployed in the proposed system powered with a Nios-2 soft-core processor. The cipher functions used in SSL-driven connection are the Scalable Encryption Algorithm (SEA), Message Digest Algorithm (MD5), Secured Hash Algorithm (SHA2). These algorithms are accelerated in the VLSI Crypto-System that is on an Altera Cyclone III FPGA DE2 development board. The experimental results shows that, by hardware acceleration of SEA, MD5 and SHA2 cryptographic algorithms, the VLSI Crypto-System performance has increased in terms of speed, optimized area and enhanced level security for the target Cybernetic application.