Mechanical integrity of vias in a thin-film package during manufacture, assembly, and stress-test

The reliability of vias used in thin film packages was estimated through analytical and numerical models. Several processes that produce thermally induced strains in the vias during manufacture, assembly (e.g., card and heat sink attach, and encapsulation of the chip), and stress-tests (e.g., T&H, ship shock, and accelerated thermal cycling) were evaluated to determine the steps which induced potentially high strains in the vias. The study consisted of two parts. In the first part, a preliminary analysis was made in which analytical estimates of via strains during the various processes were obtained under the assumptions of linear elasticity. In the second part of the study, detailed elastic-plastic finite element analyses were carried out to determine the via strains during the various processes. The models were two-dimensional, axi-symmetric in nature. In addition to uniformly plated vias, the study also included analysis of non-uniformly plated vias. In both parts of the study, via strain during a single cycle of ATC (accelerated thermal cycle) was combined with the Coffin-Manson equation for plated copper to determine the number of ATC cycles to failure. Via plating thicknesses analyzed were in the range of 0.5 to 1.4 mils. It was concluded from the study that if the via was manufacturable, then it would survive the accelerated thermal cycling test and hence the field use. This conclusion was in agreement with the results of an ATC test conducted on products with uniformly plated vias. Another conclusion from the study was that vias with non-uniform plating were unlikely to survive the rigors of the manufacturing processes