A new FPGA-based dynamic partial reconfiguration design flow and environment for image processing applications

This paper describes a new dynamic partial reconfiguration (DPR) design flow and environment for image processing algorithms. The functionality and design techniques are demonstrated through an efficient implementation of colour space conversion (CSC) intellectual property (IP) core used in many image processing applications such as compression. Furthermore, an evaluation and application flow example are presented for the CSC core. The evaluation of the proposed approach has shown the important features such as the flexibility, application connectivity, standardised interfaces, host applications and DPR area/size placement. Results obtained reveal that the proposed environment offers a better design and implementation solution using a scriptable program to establish communication between the field programmable gate array (FPGA) with IP cores such as CSC and their application, power consumption estimation for partial reconfiguration area and automatically generated the partial and initial bitstreams. The design exploration offered by the proposed DPR environment allows the generation of optimised CSC IP core in terms of area/speed ratio. For both static and reconfigurable areas, the analysis of bitstream size and dynamic power utilisation are also discussed.