DocumentCode
2307822
Title
Parallel Genetic Algorithm for VLSI Building Block Layout
Author
Xu, Ning ; Huang, Feng ; Jiang, Zhonghua
Author_Institution
Wuhan Univ. of Technol.
fYear
2006
fDate
22-24 Sept. 2006
Firstpage
1
Lastpage
4
Abstract
The VLSI building block layout (BBL) becomes a more and more important problem for VLSI physical design. In this paper, a multithread scheme for parallelizing a genetic algorithm for BBL placement optimization is presented. The parallel genetic algorithms (PGA) are realized, using sequence-pair (SP) as the representation. Parallel algorithm can be used either to speed up a problem or to achieve a higher accuracy of solutions to a problem. Our experimental results on a SUN workstation with 4 CPUs have shown that the scheme is effective in improving performance of placement over that of a sequential implementation
Keywords
VLSI; genetic algorithms; multi-threading; parallel algorithms; VLSI building block layout; multithread scheme; parallel genetic algorithm; placement optimization; sequence-pair methods; Algorithm design and analysis; Biological cells; Design methodology; Genetic algorithms; Genetic mutations; Parallel algorithms; Sun; Very large scale integration; Wire; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Wireless Communications, Networking and Mobile Computing, 2006. WiCOM 2006.International Conference on
Conference_Location
Wuhan
Print_ISBN
1-4244-0517-3
Type
conf
DOI
10.1109/WiCOM.2006.170
Filename
4149347
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