Evaluation of a 3D memory cube system

Silicon “cubes” consisting of 18-20 1 Mbit DRAM chips have been fabricated jointly by IBM and Irvine Sensors Corporation. In the stack process, the chips are joined by adhesive to form the cube, interconnected by chip metalization processes, packaged on a ceramic pin grid array (PGA) substrate that is mounted onto a memory card for testing. Modification of an existing memory card permits the substrate with cube to be substituted in place of an array of 1 Mbit DRAM memory modules that normally form the card array. Memory cube operation is verified by testing both original and cube memory card on the same memory tester. Electrical signals for each of the cards are observed and compared. Extensive electrical modeling and simulation of the cube interconnect circuitry including the chip transfer metal, interchip bus lines and PGA substrate was performed as part of the design and later verified. A high degree of interconnect and wiring redundancy was used to guarantee connection of all the chips in the cube to the applied control signals and data lines