Title :
A memory-based architecture for very-high-throughput variable length codec design
Author :
Lee, Yew-San ; Jong, Jin-Jer ; Perng, Tsyr-Shiou ; Hsu, Li-Chyun ; Jaw, Ming-Yang ; Lee, Chen-Yi
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
Variable-length code/decode (VLC/VLD) is the most popular data compression technique which can reduce the storage and communication channel bandwidth needed to transmit a large amount of data. In this paper, we present a new memory-based VLSI architecture for VLC/VLD coded system. Both coding and decoding procedures are mapped onto a memory which has been minimized by using a two-bit structure. The proposed architecture mainly consists of memory and simple arithmetic unit, making it very suitable for VLSI implementation. Simulation results show that based on 0.35 μm CMOS process, both compression rate and decompression rate up to 1.2 Gbits/s can be achieved
Keywords :
CMOS digital integrated circuits; VLSI; codecs; data compression; decoding; digital signal processing chips; encoding; memory architecture; 0.35 micron; 1.2 Gbit/s; CMOS process; DSP chip; VLSI architecture; compression rate; data compression technique; decompression rate; memory-based architecture; two-bit structure; variable length codec; very-high-throughput codec design; Arithmetic; Bandwidth; Codecs; Data compression; Decoding; Entropy; Image coding; Memory architecture; Throughput; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.621570
