A new circuit recognition and reduction method for pattern based circuit simulation

A novel circuit recognition and reduction method to extract subcircuit data corresponding to the critical paths, including all relevant parasitics and internal loading, is presented. Circuit elements extracted from layout pattern data are combined to reconstruct logic gates, and a structure of the gates is recognized by the connection between the gate terminals. The recognized circuit data is reduced by tracing signal flows and picking up the gates along the specified critical paths. The circuit elements connected between a remaining net and an eliminated net are terminated as capacitive loads, and parasitic elements are merged or eliminated when the estimated error is permissible, compared with the specified error tolerance. The error is estimated by the first-order moment of the impulse response. Results on logic macrocells and memory peripheral control circuits show that the reduced circuit sizes are 15-50 times smaller, resulting in circuit simulation speedups of 50-300 times faster