A new floorplanning method with global routing based on functional partitioning

The authors propose a floorplanning method combined with global routing for VLSI layout design. In this method, issues of types of modules, critical nets, and functional relations between modules are explicitly taken into account at both the floorplanning and the global routing stages. Thus, it is expected that the proposed method obtains the chip floorplan such that (1) the estimated chip size satisfies a given aspect ratio, (2) the estimated chip area is minimum, (3) that routing area for each critical net is reserved in the chip, and (4) each switchbox is minimally congested. It is expected that the proposed method will yield a chip floorplan with the following characteristics; the estimated chip size satisfies a given aspect ratio and is minimal; the routing area for each critical net is reserved in the chip; and each switchbox is minimally congested.<>