Title :
An area and time efficient adder for multiple additions with different word-length
Author :
Liang, Bor-Sung ; Nieh, You-Cheng ; Jen, Chein-Wei
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
To calculate multiple independent additions with different word-lengths by hardware sharing, we propose a new adder architecture in this paper, named self carry routing adder (SCRA). Multiple additions for data with different precision frequently occur in some applications, like DDA operation in 3-D graphics rendering. By segmentation, rearrangement and dynamic carry routing, the SCRA design can effectively decrease the delay time, reduce hardware area, and achieve high hardware utilization
Keywords :
CMOS logic circuits; adders; carry logic; digital arithmetic; adder architecture; area efficient adder; delay time reduction; dynamic carry routing; hardware sharing; multiple additions; rearrangement; segmentation; self carry routing adder; time efficient adder; Adders; Clocks; Costs; Delay effects; Electronic mail; Graphics; Hardware; Rendering (computer graphics); Routing; Throughput;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.621574
