DocumentCode :
2308716
Title :
The scan-DFT features of AMD´s next-generation microprocessor core
Author :
Yilmaz, Mahmut ; Wang, Baosheng ; Rajaraman, Jayalakshmi ; Olsen, Tom ; Sobti, Kanwaldeep ; Elvey, Dwight ; Fitzgerald, Jeff ; Giles, Grady ; Chen, Wei-Yu
Author_Institution :
Adv. Micro Devices, Inc., Sunnyvale, CA, USA
fYear :
2010
fDate :
2-4 Nov. 2010
Firstpage :
1
Lastpage :
10
Abstract :
There is an ever-increasing demand for higher performance microprocessors within a given power budget. This demand forces design choices - that were once seen only in high-speed custom blocks - to spread throughout the microprocessor core. These unique design structures, combined with the nanometer technology test challenges such as crosstalk, process variations, power-supply noise, and resistive short and open defects, lead to unique test challenges for today´s high-performance microprocessor core. In this paper, we present the scan architecture-related design-for-test (DFT) features and corresponding verification strategies of the nextgeneration Advanced Micro Devices (AMD) high-performance microprocessor core.
Keywords :
design for testability; microprocessor chips; design-for-test; microprocessor core; nanometer technology test; power-supply noise; process variations; scan-DFT features;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference (ITC), 2010 IEEE International
Conference_Location :
Austin, TX
ISSN :
1089-3539
Print_ISBN :
978-1-4244-7206-2
Type :
conf
DOI :
10.1109/TEST.2010.5699203
Filename :
5699203
Link To Document :
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