BIST of I/O circuit parameters via standard boundary scan

To minimize test costs for ASICs and boards, many manufacturers use reduced pin-count access and/or boundary scan-based test. Only DC parameters and basic connectivity are tested, because it takes too much engineering effort to test AC performance. This paper describes a BIST circuit that facilitates testing AC performance of I/O pins via standard boundary scan, without modifying or contacting the I/O circuitry. Process-insensitive, RTL-synthesized BIST circuitry is added outside the TAP controller. It uses a system clock and an asynchronous clock generated by a PLL in the IC to control the update and capture timing of the boundary scan cells. Silicon results show that with a typical PLL, I/O delays can be measured with adjustable precision ranging from 5 ns to 50 ps, and measurements can be compared to per-pin test limits on-chip. This permits automated test generation for I/O pin AC (and DC) parameters, and any connected board-level components, and facilitates more multi-site IC testing.