Defect-oriented cell-internal testing

Author

Hapke, F. ; Redemund, W. ; Schloeffel, J. ; Krenz-Baath, R. ; Glowatz, A. ; Wittke, M. ; Hashempour, H. ; Eichenberger, S.

Author_Institution

Mentor Graphics, Hamburg, Germany

fYear

2010

fDate

2-4 Nov. 2010

Firstpage

1

Lastpage

10

Abstract

Industry is facing very high quality requirements for today´s and tomorrow´s ICs. Especially in the automotive market these quality requirements need to be fulfilled. To achieve this we need to improve currently used test methods and fault models to improve the overall defect coverage. This paper presents two new methodologies to significantly improve this situation. One method will focus on cell-internal Bridges over a wide range of Bridge resistor values and the second method concentrates on library cell-internal high-resistive Open defects. The fault models used during the ATPG are enhanced to directly target the layout-based intra-cell Open and Bridge defects. Both methods have been evaluated on 1500 library cells of a 65nm technology. In addition the wide range of intracell Bridges has been evaluated on 10 real industrial designs with up to 60 million faults. Various results are presented from all 1500 library cells and from the 10 industrial designs as well.

Keywords

CMOS integrated circuits; automatic test pattern generation; bridge circuits; fault diagnosis; integrated circuit layout; integrated circuit testing; resistors; ATPG; CMOS IC testing; bridge resistor values; cell-internal bridges; defect coverage; defect-oriented cell-internal testing; fault models; industrial designs; layout-based intracell bridge defects; layout-based intracell open defects; library cell-internal high-resistive open defects; size 65 nm;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference (ITC), 2010 IEEE International

Conference_Location

Austin, TX

ISSN

1089-3539

Print_ISBN

978-1-4244-7206-2

Type

conf

DOI

10.1109/TEST.2010.5699229

Filename

5699229