DocumentCode :
2309159
Title :
Implementing an interval type-2 fuzzy processor onto a DSC 56F8013
Author :
Leottau, Leonardo ; Melgarejo, Miguel
Author_Institution :
Lab. for Autom., Microelectron. & Comput. Intell. LAMIC, Univ. Distrital Francisco Jose de Caldas, Bogota, Colombia
fYear :
2010
fDate :
18-23 July 2010
Firstpage :
1
Lastpage :
4
Abstract :
This paper presents the implementation of an interval type-2 fuzzy logic processor onto a Digital Signal Controller. The implementation is carried out using the improved iterative algorithm (IASCO) for type reduction. Results show the demand of hardware resources and the computational complexity of the proposed algorithm. Besides, it is presented the influence of parameters such as speed, memory use, accuracy, and resolution in the processor performance.
Keywords :
computational complexity; digital signal processing chips; fuzzy logic; iterative methods; DSC 56F8013; computational complexity; digital signal controller; improved iterative algorithm; interval type-2 fuzzy logic processor; Computational modeling; Digital signal processing; Engines; Hardware; Inference algorithms; Mathematical model; Random access memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Fuzzy Systems (FUZZ), 2010 IEEE International Conference on
Conference_Location :
Barcelona
ISSN :
1098-7584
Print_ISBN :
978-1-4244-6919-2
Type :
conf
DOI :
10.1109/FUZZY.2010.5584449
Filename :
5584449
Link To Document :
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