A programmable BIST for DRAM testing and diagnosis

This paper proposes a programmable Built-In Self-Test (BIST) approach for DRAM test and diagnosis. The proposed architecture suits well for embedded core testing as well as for stacked and stand-alone DRAMs and it provides programmability features for executing both March and NPSF-oriented test algorithms. The proposed BIST structure is designed to be easily customized with memory topology parameters such as scrambling and mirroring, in order to automatically adapt the test circuitry to the specific memory design. Experimental results show that area overhead is negligible when considering medium-large memory cuts, while executing at-speed and Back-to-Back algorithms at more than 1GHz.