DocumentCode :
2309368
Title :
Characterizing mechanical performance of Board Level Interconnects for In-Circuit Test
Author :
Reinosa, Rosa ; Allen, Aileen ; Benedetto, Elizabeth ; Mcallister, Alan
Author_Institution :
Hewlett-Packard, Palo Alto, CA, USA
fYear :
2010
fDate :
2-4 Nov. 2010
Firstpage :
1
Lastpage :
11
Abstract :
Lead Free boards are more susceptible to mechanical stress and therefore more prone to damage during manufacturing, assembly and field use. The IPC/JEDEC 9707(Spherical Bend Test Method for Characterization of Board Level Interconnects) was developed to characterize the mechanical performance of new lead free materials (i.e. laminates), board design features (i.e. pad design), and components (i.e. BGAs). This paper describes the application of the new IPC/JEDEC 9707 standard to qualify the mechanical performance of board interconnects for manufacturing and In-Circuit Test. The efforts of the International Electronics Manufacturing Initiative (iNEMI) Board Flexure Initiative Project team drove the development of this new IPC/JEDEC 9707standard.
Keywords :
bending; laminates; printed circuit design; printed circuit testing; BGA; IPC/JEDEC 9707; board level interconnect; in-circuit test; laminates; lead free board; mechanical stress; spherical bend test method;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference (ITC), 2010 IEEE International
Conference_Location :
Austin, TX
ISSN :
1089-3539
Print_ISBN :
978-1-4244-7206-2
Type :
conf
DOI :
10.1109/TEST.2010.5699252
Filename :
5699252
Link To Document :
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