Title :
High Speed Hardware for March C¯
Author :
Saha, Mousumi ; Das, S. ; Sikdar, B.K.
Author_Institution :
Dept. of Comput. Applic., Nat. Inst. of Technol., Durgapur, India
Abstract :
The variations of March tests are extensively used for functional test of SRAMs and DRAMs. This work proposes hardware realization of March C- to enable efficient fault detection in memories. The properties of single length cycle attractor cellular automata are exploited to memorize the status (faulty/non-faulty) of memory words during read (r0/r1) operation of the March C- algorithm. It effectively reduces the overhead of comparison that is required in a conventional test structure, to take decision on the faults in memory.
Keywords :
DRAM chips; SRAM chips; cellular automata; testing; DRAM; SRAM; high speed hardware; march C- algorithm; single length cycle attractor cellular automata; test structure; March tests; SACA; cellular automata; high speed memory;
Conference_Titel :
Electronic System Design (ISED), 2012 International Symposium on
Conference_Location :
Kolkata
Print_ISBN :
978-1-4673-4704-4
DOI :
10.1109/ISED.2012.56
