DocumentCode :
2309522
Title :
Standard industry components as I/O extension for an Interlock System at PITZ, MTF and XFEL
Author :
Grevsmühl, T. ; Penno, M. ; Grimberg, M. ; Jachmann, L. ; Köhler, W. ; Leich, H. ; Trowitzsch, G. ; Wenndorff, R.
Author_Institution :
DESY at Hamburg, Hamburg, Germany
fYear :
2009
fDate :
10-15 May 2009
Firstpage :
393
Lastpage :
395
Abstract :
The main task of the interlock system is to prevent any damage of the costly components of the RF station. The implementation of the interlock must also guarantee a maximum uninterrupted time of operation which implies the implementation of self diagnostics and repair strategies on a modular basis. Additional tasks include collection and temporary storage of status information of individual channels; transfer of this information to the higher level control system, and also the implementation of slow control functions. The interlock system incorporates a controller with several slave modules for I/O processing. It implements the interlock function as hardwired logic (within a FPGA) and contains a softcore processor for higher level tasks. The software performs a system-test on power-up to check the hardware functionality and the crate configuration. On success, the interlock hardware is configured for continuous operation. The architecture of the interlock system provides the fast processing of the incoming data and reaction in real time required for machine- and component-protection. Special fast front-end I/O and slave modules have been developed to achieve the timing requirements. In addition slow input signals without fast timing requirements are also processed by the central node of the interlock. For the processing of these signals there exist products on the market which are less expensive, already developed, easier to maintain, and have a long market history in comparison to our in-house solution. The integration of industrial products is possible by using a standard fieldbus protocol. For example, a possible solution based on a real time Ethernet fieldbus will be discussed. It is implemented with an "EtherCAT" master providing the I/O extension to the interlock system for industrial components.
Keywords :
accelerator RF systems; field buses; free electron lasers; nuclear electronics; EtherCAT; Ethernet fieldbus; MTF; PITZ; XFEL; interlock system; softcore processor; standard fieldbus protocol; standard industry component; Control systems; Field buses; Field programmable gate arrays; Hardware; Level control; Logic; Radio frequency; Signal processing; Software performance; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Real Time Conference, 2009. RT '09. 16th IEEE-NPSS
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-4454-0
Type :
conf
DOI :
10.1109/RTC.2009.5321640
Filename :
5321640
Link To Document :
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