A 300 K-circuit ASIC logic family CAD system

Author

Panner, Jeannie ; Abato, Richard ; Bassett, Robert ; Carrig, Keith ; Gillis, Pamela ; Hathaway, David ; Sehr, Terrence

Author_Institution

IBM Gen. Technol. Div., Essex Junction, VT, USA

fYear

1990

fDate

13-16 May 1990

Abstract

A computer-aided design (CAD) system has been developed to design CMOS application-specific integrated circuit (ASIC) logic family chips denser than any previously available, with performance comparable to bipolar technology. Design flow and key new features are described, and test chip results are given. Logic synthesis and transformation systems translate the designs to a technology-independent internal representation; optimize them for area, performance, and testability; and translate them to an implementation in the technology circuit library. The synthesis systems add logic circuits needed for testing and generate information about the clock trees used later in physical clock-free construction

Keywords

application specific integrated circuits; integrated logic circuits; logic CAD; ASIC; bipolar technology; clock trees; logic family CAD system; physical clock-free construction; technology circuit library; technology-independent internal representation; test chip results; testability; transformation systems; Application specific integrated circuits; CMOS logic circuits; CMOS technology; Circuit testing; Design automation; Integrated circuit technology; Logic circuits; Logic design; Logic testing; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124705

Filename

124705