FPGA CCSDS command decoder with BCH EDAC and level-0 command execution

This paper presents Southwest Research Institute\´s continuing development of flexible CCSDS compatible command and telemetry collection hardware. Results of the requirements analysis, systems design and hardware fabrication and test are presented in detail. The objective of this development effort was to provide an FPGA core module that could be used in a variety of spacecraft with minimal modification. The module must provide command decoding and BCH error detection and correction for the spacecraft\´s main computer. The module must also serve as a level-0 "safe" mode processor and be able to immediately execute commands received from the ground. The FPGA core module designed as a result of this effort will be used in those applications where a critical need exists for a level-0 command capability along with normal spacecraft commanding. The design may also be used to speed up system throughput by off loading the command process from the main computer\´s tasks.