Title :
An efficient and flexible bit-level systolic array for inner product computation
Author :
Wang, Chin-Liang ; Hwang, Chi-Mo
Author_Institution :
Inst. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
A bit-level bit-serial systolic array is proposed for inner product computation. If data vectors are entered continuously and interleavedly, the proposed inner product array can be fully utilized for one of two operating modes: (1) computing two independent inner products concurrently, or (2) computing the sum of two inner products or an inner product with a double size. For a given data word length B , the system yields two outputs every 2B cycles for mode 1, ie, the average throughput is one per B cycle, and one output every 2B cycles for mode 2. The feature makes the inner product array more flexible for use in applications as compared to existing related systems. FIR filters based on the array are described for demonstration of its flexibility
Keywords :
computerised signal processing; digital arithmetic; digital filters; digital signal processing chips; parallel algorithms; systolic arrays; DSP; FIR filters; average throughput; bit-level systolic array; data vectors; data word length; inner product computation; matrix multiplication; parallel algorithms; Arithmetic; Clocks; Computer architecture; Concurrent computing; Finite impulse response filter; Hardware; High performance computing; Signal processing; Systolic arrays; Throughput;
Conference_Titel :
Computer and Communication Systems, 1990. IEEE TENCON'90., 1990 IEEE Region 10 Conference on
Print_ISBN :
0-87942-556-3
DOI :
10.1109/TENCON.1990.152617