DocumentCode :
2309852
Title :
Low-cost quality assurance techniques for high-performance mixed-signal/RF circuits and systems
Author :
Chang, Hsiu-Ming ; Cheng, Kwang-Ting
Author_Institution :
Univ. of California, Santa Barbara, CA, USA
fYear :
2010
fDate :
2-4 Nov. 2010
Firstpage :
1
Lastpage :
10
Abstract :
There exist a variety of quality assurance techniques for tasks ranging from post-silicon validation, silicon debugging, manufacturing testing, in-field testing, and life time resiliency. Adding dedicated circuitry to exclusively support each task would be too costly, as each technique incurs non-trivial overheads. This paper describes three cost-effective quality assurance techniques that attempt to increase the reuse and sharing of test circuitry for multiple quality assurance tasks. First, we propose to reuse the calibration circuitry in mixed-signal/RF systems for manufacturing testing. Then, we propose the concept of application-aware testing for which application-specific criteria are used for defect screening of components. Some of the manufacturing defects which do not cause any system failures for the target applications will not be rejected and thus resulting in yield enhancement. We also develop an all-digital built-in self-test technique for mixed-signal and RF circuits that can be further used to tune the circuit performance. These techniques are demonstrated using digitally-assisted analog circuits and three-dimensional (3D) integrated designs.
Keywords :
built-in self test; calibration; integrated circuit design; integrated circuit testing; integrated circuit yield; mixed analogue-digital integrated circuits; quality assurance; radiofrequency integrated circuits; three-dimensional integrated circuits; 3D integrated design; RF circuit; all-digital built-in self-test technique; application-aware testing; calibration circuitry; defect screening; digitally-assisted analog circuits; in-field testing; life time resiliency; manufacturing defect; manufacturing testing; mixed-signal circuit; post-silicon validation; quality assurance technique; silicon debugging; test circuitry; yield enhancement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference (ITC), 2010 IEEE International
Conference_Location :
Austin, TX
ISSN :
1089-3539
Print_ISBN :
978-1-4244-7206-2
Type :
conf
DOI :
10.1109/TEST.2010.5699287
Filename :
5699287
Link To Document :
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