DocumentCode :
2309918
Title :
Panel title: 3-D test —A new paradigm in semiconductor test
fYear :
2010
fDate :
2-4 Nov. 2010
Firstpage :
1
Lastpage :
1
Abstract :
To start the session, researchers from Georgia Tech will present a target application—3-D Massively Parallel Processor with Stacked Memories. This device includes five layers including 64 processor cores, a large SRAM and three layers of an eDRAM subsystem. This device is being built at Global Foundries using their 130-nm six-metal bulk-Si process.
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference (ITC), 2010 IEEE International
Conference_Location :
Austin, TX, USA
ISSN :
1089-3539
Print_ISBN :
978-1-4244-7206-2
Type :
conf
DOI :
10.1109/TEST.2010.5699292
Filename :
5699292
Link To Document :
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