• DocumentCode
    2310231
  • Title

    Parity prediction synthesis for nano-electronic gate designs

  • Author

    Tran, D.A. ; Virazel, A. ; Bosio, A. ; Dilillo, L. ; Girard, P. ; Pravossoudovitch, S. ; Wunderlich, H.-J.

  • Author_Institution
    Lab. d´´Inf., de Robot. et de Microelectron. de Montpellier, Univ. Montpellier 2, Montpellier, France
  • fYear
    2010
  • fDate
    2-4 Nov. 2010
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    In this paper we investigate the possibility of using commercial synthesis tools to build parity predictors for nano-electronic gates designs. They will be used as redundant resources for robustness improvement for future CMOS technology nodes.
  • Keywords
    CMOS integrated circuits; nanoelectronics; CMOS technology; commercial synthesis tools; nano-electronic gate designs; parity prediction synthesis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference (ITC), 2010 IEEE International
  • Conference_Location
    Austin, TX
  • ISSN
    1089-3539
  • Print_ISBN
    978-1-4244-7206-2
  • Type

    conf

  • DOI
    10.1109/TEST.2010.5699312
  • Filename
    5699312
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2310231