Transistor Count, Chip Area and Cost Optimization of Fault Tolerant Active Pixel Sensors (FTAPS) by Modified Sensor Architecture and T-spice Based Verification of Proposed Architecture

Pixel defects are unavoidable in many solid-state image sensors, especially, CMOS image sensors. The pixel defects includes Hot pixels, Partially-stuck pixels, Fully-stuck pixels, Abnormal sensitivity defects, Random Telegraph Signal defects. Among them the most common and significant is hot pixel defect. Many approaches have been proposed to counter the effects of hot pixel defect. They include the dark frame subtraction and Fault Tolerant Active Pixel Sensor (FTAPS). This paper focuses on transistor count optimization of fault tolerant APS to achieve Chip Area And Cost Optimization by proposing a new architecture for FTAPS. It also includes verification of the response of proposed pixel architecture using TSPICE based simulations.