Title :
Effect of device and interconnect scaling on the performance and noise of packaged CMOS devices
Author :
Senthinathan, R. ; Prince, J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Abstract :
A detailed investigation of the effects of device and interconnect scaling on CMOS performance and noise was performed for multilayer packages. Results of simulations using experimental scaled-device data for one micron and two micron Leff, and recently developed modeling tools for interconnect parasitics, were obtained. These results were compared to predicted performance and noise characteristics obtained using conventional constant-voltage scaling schemes. Significant differences were found
Keywords :
CMOS integrated circuits; electron device noise; packaging; 1 to 2 micron; constant-voltage scaling schemes; device scaling; interconnect parasitics; interconnect scaling; modeling tools; multilayer packages; noise; noise characteristics; packaged CMOS devices; scaled-device data; Computational modeling; Doping; Electronics packaging; Geometry; Integrated circuit interconnections; Laboratories; MOS devices; Microstrip; Power dissipation; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124712
