Title :
A full 1.2 μm CMOS ECL-CMOS-ECL converter with subnanosecond settling times
Author :
Steyaert, M. ; Bijker, W. ; Vorenkamp, P. ; Sevenhans, J.
Author_Institution :
Katholieke Univ. Leuven, Belgium
Abstract :
A full 1.2 μm CMOS circuit which converts digital signals from ECL to CMOS and vice versa is presented. High performances are obtained due to the use of only NMOS devices in the signal path, replica biasing for accurate control of the signal levels, and charge injection to ensure extremely steep edges and subnanosecond settling times. To test and demonstrate the possibilities, a full CMOS ECL-compatible repeater for a broadband ISDN switching board has been designed: the attenuated ECL signal is converted in CMOS levels, stored in a high-speed CMOS flip-flop (which represented CMOS logic), and finally converted back into an ECL signal. The system can detect and drive 75 Ω interconnected lines as long as 15 m. The total system has two clock slices (clock and clock inverse), four data slices and one frame slice
Keywords :
CMOS integrated circuits; ISDN; digital integrated circuits; emitter-coupled logic; 1.2 micron; 15 m; 75 Ω interconnected lines; 75 ohm; B-ISDN; CMOS ECL-compatible repeater; CMOS circuit; CMOS flip-flop; CMOS to ECL converter; ECL to CMOS converter; NMOS devices; broadband ISDN switching board; charge injection; converts digital signals; four data slices; logic level converter; one frame slice; replica biasing; steep edges; subnanosecond settling times; two clock slices; B-ISDN; CMOS digital integrated circuits; CMOS logic circuits; Clocks; Flip-flops; Logic design; Logic testing; MOS devices; Repeaters; Signal design;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124713
