A Sub-Nanosecond Edge Detection System using embedded FPGA fabrics

The time to digital converter (TDC) concept is quite useful to obtain crucial timing information for nuclear radiation detection such as PET imaging applications. The high resolution nature of TDC makes them sensitive to processing and to temperature variations. Thus, a calibration procedure must often be performed to improve measurements. Moreover, field programmable gate array (FPGA)-based TDC exacerbates this problem because the transistor topology is fixed in the fabric for low cost purpose. A sub-nanosecond edge detection system able to overcome process, power supply voltage and temperature (PVT) variations was designed and implemented in an FPGA. Unlike other FPGA-based TDCs, this new solution uses embedded PVT invariant digital delay lines and deserializers included in I/O ports along with a stable clock oscillator resulting in low logic usage. The proposed approach consists in oversampling digital signals to enable absolute timestamps down to 75 ps resolution (31.85 ps rms). As a proof of concept, this paper reports timing resolution down to 321.5 ps.