Analysis of the heat removal capability of the power distribution network in 3D ICs

Three-dimensional integrated circuit (3D IC) technology has become a popular research topic to further enhance the integration scale as well as reduce the interconnection cost. However, the high power density and the poor heat conductivity of the internal layers of the 3-D structure result in high temperature and this becomes a critical design issue of 3D IC technology. Many heat removal methods have been proposed to address this problem, but most of them do not fully consider the thermal removal effect of the power distribution network (PDN). In this paper, we analyze the heat removal capability of PDN together with power through-silicon vias (PTSVs). We also compare the effect of different heat removal methods such as inserting dedicated thermal TSVs (TTSV). Our simulation shows that PDN can reduce the maximum on-chip temperature by 17%, compared with TTSV.