A fully fledged TDC implemented in field-programmable-gate-arrays

Author

Wang, Jinhong ; Liu, Shubin ; Shen, Qi ; Li, Hao ; An, Qi

fYear

2009

fDate

10-15 May 2009

Firstpage

290

Lastpage

294

Abstract

The motivation of this paper is to implement a fully fledged FPGA-based TDC in XILINX XC4VFX60 FPGAs, with the features of self-test, temperature variation compensation and trigger-matching. Self-test is performed with the statistical methods and gives the resolution of delay chain at its temperature and supplied voltage. The resolution changes with the environment temperature, and the corresponding value was recorded by self-test from 30~60degC for compensation. After compensation and INL calibration, the RMS of time measurement remains less than 30 ps per channel of the total six, and the resolution is about 50 ps. Trigger-matching is implemented using content addressable memory with the two parameters: trigger-latency and matching window programmable.

Keywords

automatic testing; compensation; content-addressable storage; field programmable gate arrays; integrated circuit testing; statistical analysis; time measurement; trigger circuits; XILINX XC4VFX60 FPGA; content addressable memory; delay chain; environment temperature; field-programmable-gate-array; fully fledged FPGA-based TDC; matching window programmable; self-test; statistical method; temperature variation compensation; time measurement; trigger-latency; trigger-matching; Built-in self-test; Delay effects; Delay estimation; Field programmable gate arrays; Lab-on-a-chip; Logic devices; Statistical analysis; Temperature distribution; Testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Real Time Conference, 2009. RT '09. 16th IEEE-NPSS

Conference_Location

Beijing

Print_ISBN

978-1-4244-4454-0

Type

conf

DOI

10.1109/RTC.2009.5321997

Filename

5321997