Leakage Current Minimization in Deep-Submicron Conventional Single Cell SRAM

The growing demand in the multimedia rich applications are motivating the low-power and high-speed circuit designer to work more closely towards the design issues arising from the design trade-offs in power and speed. This paper targets the modeling and simulation of CMOS leakage currents and its minimization approach to reduce the power consumption by a single cell SRAM cache. The popular approaches for leakage reduction are the data retention gated ground, a drowsy mode, and dynamic threshold voltage for cache. The work focuses on the simulation of a SRAM Cell for the data retention gated ground and drowsy mode SRAM Cell which shows that the current reduction of around 20% in first and 25% in second simulation model, respectively in comparison with the conventional cell with no current reduction technique.