Title :
Application of logical effort on delay analysis of 64-bit static carry-lookahead adder
Author :
Dao, Hoang Q. ; Oklobdzija, V.G.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
Abstract :
This paper presents the transistor-level analysis of the 64-bit static carry-lookahead adder (CLA). The carry blocks were implemented in two schemes: (A) 2-level and (B) multilevel. The logical effort technique was used to optimize the circuits for best performance. The analysis was verified with SPICE simulation, using 0.18 /spl mu/m, 1.8 V CMOS technology, and confirmed with small error. In addition, scheme B showed 12% improvement due to faster gate in carry block and less loading in (P,G) ones.
Keywords :
CMOS logic circuits; SPICE; adders; carry logic; circuit optimisation; multivalued logic circuits; 0.18 micron; 1.8 V; 2-level block; 64 bit; CMOS technology; SPICE simulation; circuit optimization; delay analysis; logical effort technique; multilevel block; performance; static carry-lookahead adder; transistor-level analysis; Added delay; Adders; Analytical models; Application software; CMOS technology; Circuit simulation; Delay effects; Delay estimation; Inverters; SPICE;
Conference_Titel :
Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-7147-X
DOI :
10.1109/ACSSC.2001.987705
