DocumentCode
2311369
Title
Achievement and future challenges in 3D researches
fYear
2010
fDate
20-22 Oct. 2010
Firstpage
1
Lastpage
55
Keywords
bonding processes; capacitance; chemical vapour deposition; etching; integrated circuit packaging; laser beam machining; polymers; thermal management (packaging); three-dimensional integrated circuits; transmission lines; 3D integration; 3D researches; 3D technology; 3D-optochip; CVD oxide; Cu TSV filling; TSV-based transmission lines; air gap TSV; backside via; bottom-up plating; chip-size SiP; copper bulging; critical etching control; die-wafer bonding; epifilm bonding; face-to-face bonding; gap analysis; gold stud bump; insulation material; laser drilling; low-cost TSV filling electroless Ni plating; non-3D wafer level package; parasitic capacitance; polymers; silicon interposer; thermal enhancement; thermal oxide; thin wafer handling; thin wafer handling- laser debonding; via formation; wafer-level packaging; wireless I-O; Bonding; Gallium arsenide; Heat transfer; Performance evaluation; Three dimensional displays; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
Microsystems Packaging Assembly and Circuits Technology Conference (IMPACT), 2010 5th International
Conference_Location
Taipei
ISSN
2150-5934
Print_ISBN
978-1-4244-9783-6
Electronic_ISBN
2150-5934
Type
conf
DOI
10.1109/IMPACT.2010.5699500
Filename
5699500
Link To Document