• DocumentCode
    2311516
  • Title

    Analysis of the ATLAS RPCs ROD timing performance with an embedded microprocessor

  • Author

    Aloisio, Alberto ; Capasso, Luciano ; Cevenini, Francesco ; Della Pietra, Massimo ; Izzo, Vincenzo

  • Author_Institution
    Dipt. di Sci. Fis., Univ. di Napoli Federico II, Naples, Italy
  • fYear
    2009
  • fDate
    10-15 May 2009
  • Firstpage
    76
  • Lastpage
    83
  • Abstract
    The readout data of the ATLAS´ RPC Muon Spectrometer are collected by the front-end electronics and transferred via optical fibres to the Read Out Driver (ROD) boards in the counting room. Each ROD arranges all the data fragments of one sector of the spectrometer in a unique event. This is made by the Event Builder logic, a cluster of Finite State Machines that parses the fragments, checks their syntax and builds an event containing all the sector data. In this paper we describe the Builder Monitor, developed to analyze the Event Builder timing performance. It is designed around a 32-bit softcore microprocessor embedded in the same FPGA hosting the Builder logic. This approach makes it possible to track the algorithm execution in the field. The Monitor performs real time and statistical analysis of the state machine dynamics. The microprocessor is interfaced with custom peripherals which read out the state registers, fill histograms and transfer them via DMA to the processor memory. The Builder Monitor also measures the elapsed time for each event, its length and keeps track of status and error words. We describe the hardware-software co-design of the Builder Monitor and the role played by the custom peripherals.
  • Keywords
    hardware-software codesign; nuclear electronics; particle spectrometers; position sensitive particle detectors; readout electronics; statistical analysis; ATLAS RPC ROD timing performance; ATLAS RPC muon spectrometer; FPGA hosting; Large Hadron Collider; ROD boards; algorithm execution; builder monitor; custom peripherals; data fragments; embedded microprocessor; finite state machines; front-end electronics; hardware-software co-design; optical fibres; processor memory; read out driver boards; readout data; real time analysis; resistive plate chambers; softcore microprocessor; state machine dynamics; statistical analysis; unique event; Automata; Driver circuits; Logic; Mesons; Microprocessors; Monitoring; Optical fibers; Performance analysis; Spectroscopy; Timing; Embedded processor; event building; real time monitoring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Real Time Conference, 2009. RT '09. 16th IEEE-NPSS
  • Conference_Location
    Beijing
  • Print_ISBN
    978-1-4244-4454-0
  • Type

    conf

  • DOI
    10.1109/RTC.2009.5322132
  • Filename
    5322132