DocumentCode
2311686
Title
Parallel-pipelined architecture for 2-D ICT VLSI implementation
Author
Michell, J.A. ; Ruiz, G.A. ; Burón, A.M.
Author_Institution
Dept. of Electron. & Comput., Cantabria Univ., Santander, Spain
Volume
3
fYear
2003
fDate
14-17 Sept. 2003
Abstract
The integer cosine transform (ICT) has been shown to be an alternative to the DCT for image processing. This paper presents a parallel-pipelined architecture of an 8×8 ICT(I0, 9, 6, 2, 3, 1) processor for image compression. The main characteristics of this architecture are: high throughput, low latency, reduced internal storage and 100% efficiency in all computational elements. The processor has been designed in 0.35-μm CMOS technology with an operational frequency of 300 MHz.
Keywords
CMOS integrated circuits; VLSI; data compression; discrete cosine transforms; image coding; pipeline processing; 0.35 mum; 300 MHz; CMOS technology; DCT; VLSI implementation; discrete cosine transform; image compression; image processing; integer cosine transform; parallel-pipelined architecture; CMOS process; CMOS technology; Computer architecture; Delay; Discrete cosine transforms; Image coding; Image processing; Process design; Throughput; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Image Processing, 2003. ICIP 2003. Proceedings. 2003 International Conference on
ISSN
1522-4880
Print_ISBN
0-7803-7750-8
Type
conf
DOI
10.1109/ICIP.2003.1247188
Filename
1247188
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