A CMOS analog front-end processor for an FDM system

A five channel analog front-end processor for a frequency division multiplexed (FDM) system is described. Each channel has a low-noise, two stage programmable-gain amplifier with a gain range of 15-35 dB in 1 dB steps, followed by a fifth-order elliptic switched-capacitor low-pass filter with a band edge of 300 kHz. A four-input amplifier has been designed for the first gain stage. This achieves fully balanced gain with a high input impedance. An exact design technique has been used to realize the filter. An analog multiplexer time-multiplexes the five channels with a crosstalk suppression of better than 70 dB. The chip also has a microprocessor interface, and timing and control circuitry. Fully differential topology has been used to obtain a dynamic range of 70 dB, signal-to-distortion ratio of 68 dB, and a power supply rejection ratio of 85 dB. The chip uses a 2.25 μm gate-length, 5 V technology, and has a power dissipation of only 390 mW