DocumentCode
2311839
Title
Co-Simulation of Networked Embedded System: Verification Approach
Author
Damle, Nikhil ; Keskar, A.G.
Author_Institution
Dept. of Electron. Eng., Visvesvaraya Nat. Inst. of Technol. Nagpur, Nagpur
fYear
2008
fDate
14-17 July 2008
Firstpage
187
Lastpage
188
Abstract
The paper gives an extension to the existing approach to hardware/software codesign of embedded systems by including the missed out network element commonly seen in the today´s embedded systems. The approach tries to provide a verification platform for networked embedded system. Virtual system modeling of networks & their interaction with hardware-software is the key issue in the heterogeneous co-simulation of networked embedded system.
Keywords
embedded systems; formal verification; hardware-software codesign; embedded systems; hardware-software codesign; networked embedded system co-simulation; verification approach; virtual system modeling; Application software; Embedded software; Embedded system; Hardware; Isolation technology; Microstrip; Network interfaces; Protocols; Reliability engineering; Software systems; co-simulation networrked embedded system;
fLanguage
English
Publisher
ieee
Conference_Titel
Secure System Integration and Reliability Improvement, 2008. SSIRI '08. Second International Conference on
Conference_Location
Yokohama
Print_ISBN
978-0-7695-3266-0
Electronic_ISBN
978-0-7695-3266-0
Type
conf
DOI
10.1109/SSIRI.2008.43
Filename
4579817
Link To Document